1. Field
The present invention generally relates to integrated circuit components and more specifically to capacitors.
2. Background
A variety of electrical applications make use of a capacitor structure having a plurality of capacitors that each has a first terminal and a second terminal. The capacitor structure also includes a common line connected to each of the first terminals such that the potential at each of the first terminals is about the same. The capacitor structure also includes a plurality of capacitor lines that are each connected to a different one of the second terminals such that the potential at each of the second terminals can be different. In integrated circuits, this capacitor structure can be implemented using vertical parallel plate capacitors. However, building the capacitor structure using vertical parallel plate capacitors can result in an undesirably high level of parasitic capacitance. As a result, there is a need for a reduction in the parasitic capacitance associated with the use of vertical parallel plate technology to implement the capacitor structure.